In mobile wireless equipment, the Radio Frequency (RF) transceiver and the baseband (BB) processor are often implemented on separate Integrated Circuits (IC). In such cases, the signal to be transmitted is transmitted from the baseband IC to the transceiver IC. Conversely, the received signal is transferred from the transceiver IC to the baseband processor. The transceiver IC normally contains analog signal processing, while the baseband IC shows to be predominantly digital. Therefore there are typically analog-to-digital and digital-to-analog conversions which take place in the receive and transmit paths respectively.
FIG. 1 illustrates a prior art example of a conventional block partitioning with analog IQ interface in a single antenna receive path, including an antenna 1, a filtering circuit 2, a RF transceiver 3, a baseband system 4, an RF isolator, a Power Amplifier (PA) power supply control scheme, and a PA bias control scheme. The use of an RF isolator is shown here purely as an example and is typically application specific. An isolator prevents the reflected RF power from returning to the PA output port and keeps other signals from getting into the PA output port.
Generally speaking, transceiver 3 includes analog signal processing circuitry while Base-band system 4 is fitted with powerful digital processing circuitry. Typically the analog signal processed by transceiver 3 are converted to or from digital form by a set of Analogue to Digital (A/D) and Digital to Analogue (D/A) converters respectively which, in the prior art example of FIG. 1 are located within Baseband device 4, in order to achieve the appropriate conversion of the analog signals into their digital representations and vice-versa. The exchange of IQ analog signals (each based on a differential set of wires in general) as well as the control signals including the clocks, the enable signals, and amplifiers control signals to tremendously increases the number of wires involved between the two packages. In the case of diversity receive path involving more than one antenna, the number of wires is further increased.
In the example of FIG. 1, the RF-BB interface requires as many as twenty interconnecting signals between the two chips for the antenna diversity case. This approach is currently in mass production with various semiconductor vendors for Enhanced General Packet Radio Service (EGPRS), Wideband Code Division Multiple Access (W-CDMA) (rel '99), High Speed Downlink Packet Access (HSDPA) and High Speed Uplink Packet Access (HSUPA applications).
The number of wires of an analog interface is further increased when considering the needs of the latest—and also future—developments of mobile digital communications with the advent of the latest 3GPP Long Term Evolution (LTE) features, increasing the data rate to an amount up to 100 Mbps. To achieve such values of data rate, an antenna diversity architecture is used involving a second radio receiver, further increasing the number of interconnecting wires and pins between RF transceiver 3 and baseband circuit 4.
The precise location of the A/D and D/A converters is a critical choice and dilemma for the designer of wireless mobile communication systems. Indeed, if the A/D and D/A converters are in RF transceiver 3, discrete time domain (digital) data is transferred across the interface between the baseband and the transceiver and, conversely, should the converters be incorporated within baseband device 4, then the interface would comprises continuous time domain (analog) signals.
More generally, the I/Q analog interface between RF circuit 3 and base-band circuit 4 face the following criticisms:                The large number of interconnecting pins increases packaging cost,        The large number of interconnecting signals complicates the design of the Printed Circuit Board (PCB) and final costs, especially when ground shielding is required for some wires;        Reduces the possibility of having cooperation of different circuits manufactured by different vendors;        Requires more effort in the design and redesign of the successive releases of the base-band digital circuit 4 because of the significant area of the analog blocks allocated in the integrated circuit. It has been observed, indeed, that it takes less time to design two successive releases of a pure digital integrated circuit than one circuit including a mix of digital and analog blocks.        
It has thus been observed that moving analog cells into the RF circuit is likely to fasten the time to market by allowing digital design to migrate faster to a new CMOS process node, while analog cells may not shrink as much as the digital blocks into the most adequate CMOS digital process, thus being lower cost implemented in the process used for RF design.
For the reasons above, the latest trend consists in incorporating the A/D and D/A converters within transceiver 3 in order to suppress most of the analog circuitry within the baseband circuit 4 and thus facilitate the continuous development of successive releases of that circuit.
Furthermore, since the incorporation of most of the remaining analog components within the RF transceiver leads to a fully digital interface between both the transceiver 3 and the baseband device 4, there is given an opportunity to develop a standardized digital interface allowing easy communication between components designed and manufactured by different manufacturers.
FIG. 2 is an example of the implementation of a diversity receive path comprising antennas 11, filters 12, a RF transceiver 13 communicating with a baseband 14 through a purely digital interface 15. It can be seen that the A/D and D/A converters are now located within the RF transceiver 13.
Such architecture also has the significant advantage—also justifying the strong interest from the manufacturers—of decreasing the number of wires between the two systems because of the serialization/de-serializing process carried out at the level of the digital interface 15.
Such decrease of the number of wires clearly facilitates the design of and reduces the manufacturing costs of the components.
Generally speaking, the manufacturers of mobile wireless telecommunications products have initiated discussions and collective work for standardizing the digital interface between the RF transceiver and the BB deviceCombining the terms “digital” and “RF” together into the name “DigRFSM”, this interface is already in its third evolutionary step as listed in Table 1.
TABLE 1DigRF version evolutionsDigRF SM Interface bitrateversionStandard(Mbit/s)v2: 2GGSM/GPRS/EDGE 26V3: 3G2G + HSPA312v4: 4G3G + LTE1248, 1456, 2498, 2912
The more recent version of DigRFSM v4 uses a unified physical layer from M-PHY work group of the MIPI (Mobile Industry Processor Interface) consortium. DigRFSM, leading to an improved digital interface based on only 6 physical wires interfacing RF and BB IC and allowing high level of programming abstraction to improve interoperability across vendors.
To the contrary to the analog interface wherein the data and the control were conveyed through different wires, the new DigRF digital interface caries data and control messages which are transmitted through one unique serialized pair of differential lanes. In TX, only one pair of differential lanes is used to carry both control and data message. Similarly, data messages are now digital symbols also being serialized.
In DigRFSM, there are currently 4 interface speed clock frequencies being considered to latch the data onto the serial lanes:                2912 MHz, leading to 2912 Mbit/s transfer rate, referred to High Speed 2 (HS2)        2496 MHz, referred to High Speed 1 (HS1),        1456 MHz, referred to Low Speed 2 (LS2),        1248 MHz, referred to Low Speed 1 (LS1).        
While the DigRFSM presents a significant improvement in the interface between RF and BB devices, there is still a significant problem to be considered.
Indeed, the use of the Digital Interface between both RF and BB systems entails the introduction of digital noise within an analog IC, and particularly in its most sensitive part: the Low Noise Amplifiers (LNA), thus adding additional noise which is likely to desensitize the receiver.
Indeed, a pair of DigRFSM line generate broadband white noise over several hundred of MHz, noise which is coupled into the LNA input pin(s) via electromagnetic coupling of the long bonding wires which can be modeled as radiating transmissions lines, acting in a fashion very similar to antennae.
The LNA sets the receiver chain added noise over thermal noise, commonly referred to the Noise Figure (NF). Due to its extremely low noise, it takes only very little added noise to degrade the RF receiver intrinsic noise floor. For example, assuming an RF IC with a 3 dB intrinsic NF referred to its LNA input pin (ie. an equivalent noise floor of −171 dBm/Hz at 25 degree Celsius), the maximum additional amount of noise being tolerable to degrade the intrinsic NF by 0.5 dB is as low as −180.1 dBm/Hz since −180.1+171=−170.5 dBm/Hz (equivalent to 3.5 dB NF). The lower the RF receiver intrinsic NF, the lower is the maximum tolerable noise for a given desensitization.
This relationship is summarized in FIG. 3 illustrating the radio receiver desensitization vs. a given additional white noise source power spectral density (PSD in dBm/Hz) for 4 different intrinsic NF: squares, NF=8 dB, diamonds, NF=6 dB, triangles, NF=4 dB, circles, NF=2 dB
It can be seen that in the case of the GPS application with an intrinsic NF=2 dB, a 0.3 dB desensitization leads to a maximum additional white noise source PSD at the LNA input of −184 dBm/Hz.
FIG. 4 is a table which summarizes the maximum allowable noise for LNA depending on the different bands.
Clearly, the LNA most sensitive LNA is in GPS receivers since the signal is very low.
The observations below show how critical might be the introduction of additional noise resulting from a digital interface in the most sensitive parts of the analog circuitry, and particularly in the case of a GPS receiving path.
Some solutions are already known for limiting the effects of such additional noise.
A first solution consisting in carefully designing the LNA by systematically using differential wires in order to take benefit of the common mode rejection of such a differential architecture.
Furthermore the use of a sophisticated packages (eg. so-called flip chip package) for embodying the RF transceiver integrated circuit may reduce the coupling between the input wire of the LNAand the digital interface, which coupling generally increases with the frequency.
All those techniques clearly tend to increase the design and manufacturing costs of the transceiver IC.
In some situations, those techniques do not allow to avoid desensitization of the receiver in some circumstances.
In particularly, it has been shown that a 1248 MHz clock rate of the DigRFSM v4 interface desensitize the GPS receiver and gives very little margin for operating the LNA on bands above 1700 MHz.
The problem results from the fact that a high rate digital interface is introduced in highly sensitive analog circuits and the LNA therein included, which generates a significant amount of digital noise spoiling the low noise amplifiers.
This is the problem which is addressed by the invention.